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NCP5612 High Efficiency Ultra Small Thinnest White LED Driver
The NCP5612 product is a dual output LED driver dedicated to the LCD display backlighting. The built-in DC/DC converter is based on a high efficient charge pump structure with operating mode 1x and 1.5x. It provides a peak 87% efficiency together with a 0.2% LED to LED matching.
Features http://onsemi.com MARKING DIAGRAM
LLGA12 (2x2 mm) MU SUFFIX CASE 513AA YD M G G
* * * * * * * * * * *
Support the Single Wire Serial Link Protocol Peak Efficiency 90% with 1x and 1.5x Mode Programmable Dimming ICON Function Built-in Short Circuit Protection Provides 16 steps Current Control Controlled Start-up Inrush Current Built-in Automatic Open Load Protection Tight 0.2% Matching Tolerance Accurate 1% Output Current Tolerance Smallest Available Package on the Market This is a Pb-Free Device
1
YD = Specific Device Code M = Date Code G = Pb-Free Package (Note: Microdot may be in either location)
PIN CONNECTIONS
Typical Applications
GND C1N LED1 LED2 IREF CNTL 220 nF/10 V 220 nF/10 V NC 1 mF/10 V C4 GND 7 Device LWY87S D1 LED1 LED/ICON U1 NCP5612 2 3 LWY87S D2 NCP5612MUTBG Package LLGA12 (Pb-Free) Shipping 3000/T ape & Reel 2 3 4 5 6 (Top View) 1 12 11 Vbat 10 C1P 9 8 7 C2N C2P VOUT
* Portable Back Light * Digital Cellular Phone Camera Photo Flash * LCD and Key Board Simultaneous Drive
VCC C5 1 mF/6.3 V C3 1 mF/6.3 V C1 C2 12 10 9 8 C1N C1P C2N C2P 11 VCC-cpu I/O pin MCU GND GND R1 10k 1 6 5 4 Vbat NC CNTL IREF GND Vout Vbat
GND
ORDERING INFORMATION
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Figure 1. Typical Single Wire White LED Driver
(c) Semiconductor Components Industries, LLC, 2006
1
August, 2006 - Rev. 0
Publication Order Number: NCP5612/D
NCP5612
C1 220 nF 12 10 9 C2 220 nF 8 C4 1 mF/10 V Vbat GND C3 11 1 mF/6.3 V GND
CHARGE PUMP DC/DC CONVERTER
7
Vout
OVERVOLTAGE CNTL LWY87S 5 150 k Vbat GND R1 4 10 k GND 1 CURRENT MIRRORS Vbat D1 2 LWY87S D2
DIGITAL CONTROL
Q1
Q2 3
ANALOG CONTROL
GND GND NC 6 OVERTEMPERATURE
Figure 2. Simplified Block Diagram
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NCP5612
PIN FUNCTION DESCRIPTION
Pin No. 1 Symbol GND Function POWER Description This pin is the GROUND signal for the power analog blocks and must be connected to the system ground. This pin is the GROUND reference for the DC/DC converter and the output current control. The pin must be connected to the system ground, a ground plane being strongly recommended. This pin sinks to ground and monitors the current flowing into the first LED, intended to be used in backlight application. The current is limited to 30 mA maximum (Note 2). The LED1 is deactivated when the ICON bit of the LED-REG register is High. The LED1 is automatically disconnected when an open load is sensed pin 2 during the operation. This pin sinks to ground and monitors the current flowing into the second LED, intended to be used in backlight application. The current is limited to 30 mA maximum (Note 2). The LED2 fulfills the ICON function, LED1 being deactivated, when the ICON bit of the LED-REG register is High. The LED2 is automatically disconnected when an open load is sensed pin 3 during the operation. This pin provides the reference current, based on the internal band-gap voltage reference, to control the output current flowing in the LED. A 1% tolerance, or better, resistor shall be used to get the highest accuracy of the LED biases. An external current source can be used to bias this pin to dim the light coming out of the LED. In no case shall the voltage at pin 4 be forced either higher or lower than the 600 mV provided by the internal reference. This pin supports the flow of data between the external MCU and the NCP5612 internal registers. The protocol makes profit of a Single Wire structure associated to a Serial 8 bits format data flow. No internal connection This pin provides the output voltage supplied by the DC/DC converter. The Vout pin must be decoupled to ground by a 1 mF ceramic capacitor located as close as possible to the pin. Cares must be observed to minimize the parasitic inductance at this pin. The circuit shall not operate without such bypass capacitor connected across the Vout pin and ground. The output voltage is internally clamped to 5.5 V maximum in the event of no load situation. On the other hand, the output current is limited to 40 mA (typical) in the event of a short circuit to ground. One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C2N (Note 1) One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C2P (Note 1) One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C1N (Note 1) Input Battery voltage to supply the analog and digital blocks. The pin must be decoupled to ground by a 1.0 mF minimum ceramic capacitor. One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C1P (Note 1)
2
LED1
INPUT, POWER
3
LED2
INPUT, POWER
4
IREF
INPUT, ANALOG
5
CNTL
INPUT, DIGITAL
6 7
NC VOUT
- OUTPUT, POWER
8 9 10 11 12
C2P C2N C1P VBAT C1N
POWER POWER POWER INPUT, POWER POWER
1. Using low ESR ceramic capacitor, 50 mW maximum, is mandatory to optimize the Charge Pump efficiency. 2. Total DC/DC output current is limited to 60 mA.
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NCP5612
MAXIMUM RATINGS
Rating Power Supply Output Power Supply Digital Input Voltage Digital Input Current Human Body Model: R = 1500 W, C = 100 pF (Note 3) Machine Model LLGA12 Package Power Dissipation @ TA = +85C (Note 4) Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Air Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Latch-up Current Maximum Rating per JEDEC Standard: JESD78 Moisture Sensitivity (Note 5) Symbol VBAT Vout CNTL ESD Value 7.0 7.0 -0.3 < V < VBAT 1.0 2.0 200 200 51 200 -40 to +85 -40 to +125 +150 -65 to +150 "100 1 Unit V V V mA kV V mW C/W C/W C C C C mA
PD RqJC RqJA TA TJ TJmax Tstg - -
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) "2.0 kV per JEDEC standard: JESD22-A114. Machine Model (MM) "200 V per JEDEC standard: JESD22-A115. 4. The maximum package power dissipation limit must not be exceeded. 5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J-STD-020A.
POWER SUPPLY SECTION (Typical values are referenced to TA = +25C, Min & Max values are referenced -40C to +85C ambient temperature, operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.)
Rating Power Supply Continuous DC Current in the Load @ Vf = 3.8 V, 3.2 V < Vbat < 5.5 V, ICON = L (30 mA per LED) Output ICON Current (ICON bit = H) @ 3.2 V < Vbat < 4.2 V, TA = +25C Continuous Output Short Circuit Current Output Voltage Compliance (OVP) DC/DC Start Time (Cout = 1.0 mF) from end of the CNTL Tdst delay to full load operation, @ Vbat = 3.6 V Output Voltage Turn-off (Cout = 1 mF) From Last Low Level at CNTL pin to Vout = 5% Standby Current, 0C < TA < +85C Vbat = 3.6 V, Iout = 0 mA, ICON = L Operating Current, @ Iout = 0 mA, ICON = H, Vbat = 3.6 V Output LED to LED Current Matching, Vbat = 3.6 V, ILED = 10 mA, LED1 & LED2 are Identical -25C < TA < 85C Output Current Tolerance @ Vbat = 3.6 V, ILED = 10 mA -25C < Ta < 85C Charge Pump Operating Frequency Thermal Shutdown Protection Thermal Shutdown Protection Hysteresis Efficiency - LED1 = LED2 = 10 mA, Vf = 3.2 V, Vbat = 3.8 V (Total = 20 mA) Efficiency - LED1 = LED2 = 30 mA, Vf = 3.75 V, Vbat = 3.8 V (Total = 60 mA) Pin 11 7 7 7 7 12 12 11 11 2, 3 2, 3 - - - - - Symbol Vbat Iout 60 IICONTOL Isch Vout Tstart Toff Istdb Iop IMAT ITOL Fpwr TSD TSDH EPWR - - 4.8 - - - - - - - - - - - - 450 40 - 150 500 - 600 "0.2 "1.0 1.0 160 30 87 84 - 550 100 5.7 - - 1.0 - "1.0 - - - - - - mA mA V ms ms mA mA % % MHz C C % Min 2.7 Typ - Max 5.5 Unit V mA
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NCP5612
ANALOG SECTION (Typical values are referenced to TA = +25C, Min & Max values are referenced -40C to +85C ambient
temperature, operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.) Rating Reference Current @ Vref = 600 mV (Note 7) Reference Voltage (Note 7) 0C < TA < +85C Base Reference Current (IREF) Current Ratio Pin 4 4 - Symbol IREF VREF ILEDR Min 1.0 -3% - Typ - 600 500 Max 60 +3% - Unit mA mV -
6. The overall output current tolerance depends upon the accuracy of the external resistor. Using 1% or better resistor is recommended. 7. The external circuit must not force the IREF pin voltage either higher or lower than the 600 mV specified.
DIGITAL PARAMETERS SECTION (Typical values are referenced to TA = +25C, Min & Max values are referenced -40C to +85C ambient temperature, operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.) Note: Digital inputs undershoot < - 0.30 V to ground, Digital inputs overshoot < 0.30 V to VBAT.
Rating Positive going Input High Voltage Threshold, CNTL signals Negative going Input Low Voltage Threshold, CNTL signals Pull Down Resistor Delay between two consecutive frame (Note 9) Wake up delay (Note 9) CNTL signal rise and fall time (Note 9) Clocked CNTL High (Note 9) CNTL Low (Note 9) CNTL Store data delay (Note 9) Input CNTL frequency (Note 9) 8. see Timings Reference 9. Parameter not tested in production, guaranteed by design. Pin 5 5 5 5 5 5 5 5 5 5 Symbol VIH VIL Rcntl tidle twkp tr, tf ton ton, toff Tdst FCNTL Min 1.4 - - 10 - - - 1.0 - - Typ - - 150 - - - - - 200 - Max VBAT 0.6 - - 1.0 200 75 - 300 400 Unit V V kW ms ms ns ms ms ms kHz
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NCP5612
APPLICATION INFORMATION
ton twkp tf 90% VIH tr 90% toff
VIL Bit = 1
10% Bit = 0 Bit = 0
Figure 3. Timings Reference
VOH @ Vccio = 3.0 V 2600 mV VOH @ Vccio = 2.6 V 2400 mV
1400 mV VOL @ MOTOROLA: 500 mV VOL @ QUALCOMM: 450 mV VOL @ INTEL: 400 mV
VIHsw
VIL
600 mV
100 mV/step
GROUND
Figure 4. Basic Cellular Phone Chip Set Digital Output Levels
DC/DC Operation The converter is based on a charge pump technique to generate a DC voltage capable to supply the White LED load. The system regulates the current flowing into each LED by means of internal current mirrors associated with the white diodes. Consequently, the output voltage will be equal to the Vf of the LED, plus the drop voltage (ranging from 150 mV to 400 mV, depending upon the output current and Vbat / Vf ratio) developed across the internal NMOS mirror. Typically, assuming a standard white LED forward biased at 10 mA, the output voltage will be 3.6 V. The built-in OVP circuit continuously monitors the output voltage and stops the converter when the voltage is above 5.0 V typical. The converter resumes to normal operation when the voltage drops below the typical 5.0 V (no latch-up mechanism). Consequently, the chip can operate with no load during any test procedures.
Load Current Calculation
The load current is derived from the 600 mV reference voltage provided by the internal Band Gap associated to the
external resistor connected across IREF pin and Ground (see Figure 5). In any case, no voltage shall be forced at IREF pin, either downward or upward. The reference current is multiplied by the internal current mirror, associated to the number of pulses as depicted Figure 9, to yield the output load current. Since the reference voltage is based on a temperature compensated Band Gap, a tight tolerance resistor will provide a very accurate load current. The resistor is calculated from the Ohm's law (Rbias = Vref/IREF) and define the maximum current flowing into the LED when 20 pulses have been counted at the CNTL pin. Since the reference current must be between the minimum and maximum specified, the resistor value will range between Rbias = 300/30 mA = 10 kW and Rbias = 300/0.5 mA = 600 kW. Obviously, the tolerance of such a resistor must be 1% or better, with a 100 ppm thermal coefficient, to get the expected overall tolerance. Typical applications will run with Rbias = 10 kW to make profit of the full dynamic range provided by the S-Wire DATA byte.
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NCP5612
VBandGap
LED Return Pin 2 & 3 600 mV
R1 GND
IREF
Pin 4
GND
Note: the IREF pin must never be biased by an external voltage.
Figure 5. Basic Reference Current Source Load Connection
The NCP5612 is capable to drive the two LED simultaneously, as depicted (see Figure 1), but the load can be arranged to accommodate one or two LED if necessary
NCP5612 7 LWY87S
in the application (see Figure 6). In this case, the two current mirrors can be connected in parallel to drive a single powerful LED, thus yielding 60 mA current capability in a single LED.
NCP5612 7 LWY87S D1 LWY87S D2 2 C4 1 mF/6.3 V
D1 2
C4
1 mF/6.3 V
GND 3 3
GND
Figure 6. Typical Single and Double LED Connections
Finally, an external network can be connected across Vout and ground, but the current through such network will not be regulated by the NCP5612 chip (see Figure 7). On top of that, the total current out of the Vout pin shall be limited to 60 mA.
C4 NCP5612 GND 7 LWY87S D1 20 mA 2 LWY87S D2 20 mA R1 220R 3 GND 5mA R2 220R D3 5mA LWY87S D4 LWY87S 1uF/6.3V
Single Wire Serial Link Protocol
The proposed S-WIRE uses a pulse count technique already existing in the data exchange systems. The protocol supports broken transmission, assuming the hold time is shorter than the maximum 200 ms typical specified in the data sheet. The S-WIRE details are provided in the AND8264 application note. Based on the two examples provided in Figure 8, the CNTL pin supports two digital level: CNTL = Low the system is shut-off and no current flow in either LED1 or LED2. CNTL = High the system is active and the two LED are powered according to the selected sequence. There is no time delay associated with the Low state and the LED are switched Off when the CNTL signal drops to Low. To program a new LED configuration, one shall send the number of pulses on the CNTL pin according to the true table: * The internal counter is reset to zero on the first negative going transient present on the CNTL pin
Figure 7. Extra Load Connected to Vout
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NCP5612 * The first four positive going pulses are used to control
the ICON (LED2): 1. Pulse #1 ICON = 100 mA 2. Pulse #2 ICON = 150 mA 3. Pulse #3 ICON = 250 mA 4. Pulse #4 ICON = 450 mA The fifth positive pulse will clear the ICON and activate the normal operation of LED1 and LED2 The pulses from the fifth to the twentieth will increase the LED current according to a pseudo logarithmic scale (see Figure 9). Any pulses beyond the twentieth will not make change to the LED current if the delay between the pulses is shorter than 75 ms.
* The system returns to zero if a pulse, delayed by
* * *
200 ms - Tdst - , follows the twentieth one and the cycle restart from the beginning. Once the expected LED current value is reached, the CNTL pin must stay High to store the new data and maintain the LED active. The contain of the counter is stored into the internal LED registers at the end of the built-in 200 ms typical delay: no action will take place during the end of the last positive going pulse and the end of the Tdst delay. Such a protocol prevent the system for broken transmission. On the other hand, in order to avoid corrupted data transmission, the High level shall be 75 ms maximum during a given data frame. Consequently, the pulse frequency is bounded by a 13 kHz minimum and a 400 kHz maximum.
Start Bit Negative going edge Clear counter Example #1: CNTL LED1= 0 mA LED2 = ICON Pulse count
Tdst
TEL
1
2
3 Shut down mode LED1=LED0= 0 mA Tdst
ICON = 250 mA TEHmax 75 ms when clocked Example #2: CNTL LED1= 6 mA LED2 = 6 mA Pulse count
TEH
1
2
3
4
5
6
7
8
9
10 Tdst
ICON = disabled Example #3: CNTL LED1= 30 mA LED2 = 30 mA Pulse count 1 Note: timings are not scaled.
LED1=LED2 = 6 mA
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 LED1=LED2 = 30 mA LED1=LED2 = 0 mA
ICON = disabled
Figure 8. Basic NCP5612 Programming Sequence
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NCP5612
DIMMING The built-in Single Wire Serial Link interface provides a simple way to accurately control the output current flowing in the two LED. Provision have been made, at silicon level, to provide a full dimming of the backlight (NORMAL mode of operation), the ICON current being adjustable in four steps when it is activated.
Table 1. LED Dimming Configuration
Pulse Count Pulse 1 Pulse 2 Pulse 3 Pulse 4 Pulse 5 to Pulse 20 LED activity LED#2 = 100 mA, LED#1 de-activated LED#2 = 150 mA, LED#1 de-activated LED#2 = 250 mA, LED#1 de-activated LED#2 = 450 mA, LED#1 de-activated ICON de-activated, NORMAL backlight takes place 35 30 25 IOUT (mA) 20 15 10 5.0 0 0 5.0 10 BIT CLOCK 15 20 IOUT = F(Bit Clock) (linear scale) Bit Clock 1 2 3 4 5 6 7 8 I-LED(mA) 1 2 3 4 5 6 8 10 Bit Clock 9 10 11 12 13 14 15 16 I-LED(mA) 12 14 16 19 22 25 28 31
The DC/DC converter is switched OFF and the two LED are disconnected when LED-REG=$00. When the ICON mode is activated, the DC/DC converter is switched OFF, LED#1 is deactivated from the LED current sense and the programmed bias current (powered from the Vbat source) is forced into LED#2.
Figure 9. Typical Output Current Slope
Figure 10. Typical Efficiency
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NCP5612
Figure 11. Typical LED to LED Current Matching
C1 VBAT 4.7 mF/10 V GND C2 12 11 TP1 DATA 6 5 DATA 4 IREFBK R1 10 k Z1 GND GND 1 Vbat NC CNTL IREF GND LED1 LED/ICON 2 LED1 3 LED2 LWY87S D2 D1 LWY87S U1 NCP5612 10 9 Vout C3 C4 8 7 VOUT GND 1.0 mF/10 V 220 nF/6.3 V 220 nF/6.3 V TP2 VOUT
J1 2 1 POWER GND J2 2 4 6 8 10 1 3 5 7 9
C1N C1P C2N C2P
S-WIRE PORT GND
Figure 12. Demo Board Schematic Diagram
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NCP5612
PACKAGE DIMENSIONS
LLGA12 MU SUFFIX CASE 513AA-01 ISSUE O
D A B
PIN ONE REFERENCE
E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.50 0.60 0.00 0.05 0.15 0.25 2.00 BSC 0.80 1.00 2.00 BSC 0.55 0.65 0.40 BSC 0.25 --- 0.30 0.50 0.40 0.60
2X
0.10 C
2X
0.10 C 0.10 C
12X
0.08 C
SEATING PLANE
A1
11X
L K
1
e/2
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CCCC CCCC CCCC
L1
2 12 11
TOP VIEW
A SIDE VIEW C D2
6
SOLDERING FOOTPRINT*
e
9X
0.66
2.30
1
12X
0.23 0.40 PITCH
E2
2.06 0.93 0.91
7
12X
b BOTTOM VIEW
0.10 C A B 0.05 C
NOTE 3
11X
0.56
0.63
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP5612/D

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